Device Design and Packaging Award

Makers of flagship smartphones seek to squeeze the highest levels of functionality and performance into ultra-slim handsets. Because these high-end phones are designed for global or super-regional use they also need to integrate support for many different regional LTE bands as well as multiple carrier aggregation (CA band combinations.

The RF Fusion portfolio of solutions from Qorvo contains multiple high-performance modules focused on differentiated performance – achieved by integrating Qorvos leading technologies such as NoDrift and LowDrift filters along with advanced power amplifier (PA and switch technologies. All delivered in the industrys smallest form factors. Qorvo’s RF Fusion provides OEMs with a complete RF Front End (RFFE solution that incorporates all major transmit and receive functionality including support for major frequency bands into three compact modules covering the high-band mid-band and low-band regions of the spectrum. The architecture is also designed to integrate support for the rapid deployment of CA in markets worldwide. .

Many applications require isolated power supplies protected from electromagnetic interferences (EMI noise. Strong galvanic isolation is necessary against lightning high voltages ground faults EMI and RF noises. This present constraining challenges for utilities transmission towers medical automotive and telecom equipment manufacturers. For example, more compact Power Control Units (PCU capable of delivering more isolated power are required to increase the range of electric vehicles). Prior-art transformer-based technologies can be bulky and insufficient for demanding EMI control. Next Gen isolated power supply solutions are necessary for this rapidly growing market. Power Over Fibre applications require more available power and higher efficiencies.

Azastra has developed and commercialized a product featuring the highest optical to electrical conversion efficiency ever. The devices are based on ultra-thin GaAs p/n junction engineered with a Vertical Epitaxial Heterostructure Architecture (VEHSA design. The photovoltaic VEHSA design allows achieving a near-optimum responsivity an improved photovoltage output compared to p/n junctions with standard thicknesses and low series resistance and shunting effects are yielding high fill-factor values. The innovation enables not only unprecedented performance but also tailored output voltages adapted for various applications using the optical power of laser diodes. The photovoltaic Power Converter devices have been demonstrated commercially with Electrical Output of up to 5.9W and efficiencies 65 percent. That is about double the performance and 10X the output power of other commercially available laser power converters. An open circuit voltage enhancement of 92 mV per junction is measured compared to devices with a side by side planar architecture. The devices exhibit a near optimum responsivity of up to 0.645 A/W. It corresponds to an external quantum efficiency of ~94 percent. Photon coupling effects are found to broaden the spectral range for which the VEHSA devices convert high-power optical laser inputs with high efficiencies into a usable electrical output having a pre-set voltage between ~5 V and ~24 V. The nanoscale junctions each generating about 1.2 V of output voltage. Record-high photovoltages have been obtained with the VEHSA implementation of 20 such thin junctions (PT20. Photovoltages in excess of 23 V have been measured for a continuous wave monochromatic optical input power of about 1W tuned in the 750 nm to 875 nm wavelength range. Efficiencies greater than 60 percent have been demonstrated for the entire PTN family. For the PT20 structure the narrowest ultrathin base was achieved with a thickness of only 24 nm.

Wolfspeed’s new high performance SiC power module utilizes the standard 62 mm mounting pattern but reimagines the remaining package to provide higher maximum current capability higher power density and lower inductance than previous SiC modules. These packaging innovations enable significant volumetric and power density improvements previously unimaginable for traditional power electronics systems such as those used in industrial aerospace and automotive motor drive applications. To harness the high temperature and low loss capabilities of SiC in this device Wolfspeed developed a unique low-inductance high-temperature multi-chip power module package around their SiC MOSFETs to enable operation up to a maximum junction and ambient temperature of 175°C which far exceeds the maximum temperature capability attainable with silicon (Si IGBT modules. The high-performance package incorporates a low parasitic design resulting in just 5nH of power loop inductance for ultra-high-speed switching which is a 2–5x reduction over traditional modules. The novel package design also allows users to tailor the number of SiC MOSFETs and diodes per switch position without a packaging redesign. The CAS325M12HM2’s standard half-bridge configuration is seven Gen2 1200V 25mΩ MOSFETs with six 1200V 50A anti-parallel Schottky barrier diodes per switch position. However, the device configuration and topology can be tailored to meet the customer’s performance targets by accommodating up to 12 Gen2 1200V 25mΩ MOSFETs per switch position. The 1200V/325A power module exhibits extremely low on-resistance of 4mΩ at room temperature and less than 8mΩ at 175°C junction temperature ensuring that the module exhibits low losses over temperature. The ultra-fast switching performance of the power module features 50ns rise and fall times with extremely little overshoot due to the ultra-low parasitic design.


Substrates and Materials Award

Disco Corporation, has developed a laser ingot slicing method called Kabra (Key Amorphous-Black Repetitive Absorption) for high-speed production of SiC wafers. The existing methods for slicing wafers from a SiC ingot typically use diamond wire saws. The processing time is long due to the high rigidity of SiC. Moreover, the number of wafers produced is small due to the amount of material lost in the slicing sections. The Kabra process forms a flat light-absorbing separation layer at a specified depth by irradiating a continuous, vertical laser from the upper surface of the SiC and creating wafers.

According to Disco, this laser slicing method relies on the fact that SiC can be decomposed by a focused laser and separated into amorphous silicon and carbon; and that the light absorption coefficient of the black amorphous material is approximately 100,000 times larger than that of SiC.

Existing processes require around two hours to slice a wafer from a 4-inch SiC ingot (two to three days for one ingot). In contrast, the Kabra process requires only 25 minutes to slice a wafer (around 18 hours for one ingot). In addition, this process only takes around 30 minutes to slice a wafer from a 6-inch SiC ingot even though the existing process requires over three hours.

Element Six’s TM200 is the highest thermal conductivity bulk heat spreader material available in the market with room temperature thermal conductivity 2000 W/mK (more than 5x copper or 10x other commonly used ceramic materials. Element Six has developed specialized chemical vapor deposition (CVD processes to produce free standing diamond substrates that deliver this market leading thermal conductivity. Designed to enable extreme performance thermal packaging for use in high power or high power density devices TM200 enables increased power and reliability and reduced system size.

The spreading of heat within TM200 is highly isotropic spreading the heat with equal efficiency in a planar direction as well as through the material. It is produced in diameters up to 5 inches. A crucial element in developing any new disruptive technology is the control of the engineering of the basic building blocks.

Chemical vapor deposition (CVD grown diamond as a high performance heat spreader is considered an enabling material for a wide range of disruptive electronics from gallium nitride (GaN solid state RF X-band power amplifiers (PAs to advanced application-specific integrated circuits (ASICs to laser diodes. Understanding the engineering of the thermal properties of grown diamond is an essential part of any such building blocks. While there are CVD diamond growth chemistries that continue to promote re-nucleation to avoid grain size development for TM200’s thermal conductivity it is imperative to choose conditions producing excellent crystal quality consistent with:

  • Exceptional intra grain purity with respect to point and extended defect
  • Exceptionally well inter-grown and low defect density grain boundaries
  • Large grains augmented with significant levels of post synthesis processing the ultimate product delivers precision manufactured parts incorporated in a platform that delivers more than 2000 W/mK thermal conductivity with 10M12 Ω-cm bulk and 1010 Ω-cm surface resistivity at high volume.


High-volume Manufacturing Award

Lam Research has introduced atomic layer etching (ALE capability to its Flex dielectric etch systems). Enabled by Lam’s proprietary Advanced Mixed Mode Pulsing (AMMP technology the new ALE process has demonstrated the atomic-level control needed to address key challenges in scaling logic devices to 10 nm and below.

From transistor and contact creation to interconnect patterning logic, manufacturers require a new level of precision in order to continue scaling beyond 10 nm. Today conventional technologies do not provide sufficient control for the stringent specifications demanded for device-enabling applications such as self-aligned contacts where etch creates the critical structures. Only Flex with AMMP technology allows for SAC without the process trade-offs.

The Flex system is the first in the industry to use plasma-enhanced ALE in production for dielectric films. Enabled by Lam’s proprietary AMMP technology the ALE technology results in a two times improvement in selectivity over previous dielectric etch technologies while delivering atomic-level control.

Last year Oxford Instruments announced the development of a SiC via plasma etch process using its PlasmaPro100 Polaris system.

SiC is becoming an increasingly important material, particularly for high performance GaN RF devices using SiC as a substrate. A smooth via etch through the SiC is essential to the functioning of these devices.

Capabilities of Oxford Instruments' SiC via process include high SiC etch rate enabling maximum throughput; smooth sidewalls for problem free post etch metallisation; and high selectivity to underlying GaN layer giving a smooth, low damage stop onto the GaN device layers.

Other features include clamping of sapphire carriers using Oxford Instruments' unique patented Electrostatic Clamp technology ensuring good sample temperature control and maximum yield; the capability of etching SiC and GaN in the same tool through advanced plasma source technology; and high utilisation provided by long Mean Time Between Cleans (MTBC).

Advancing semiconductor technology, X-FAB Silicon Foundries put itself at the vanguard of wide-bandgap semiconductor production last year by announcing the availability of its silicon carbide (SiC) offering from its wafer fab in Lubbock, Texas.

Thanks to major internal investments in the conversion of capital equipment, as well as the support provided by the PowerAmerica Institute at NC State University, X-FAB Texas has heavily upgraded its manufacturing resources in order to make them "SiC-ready"”". Among the tools now added are a high-temperature anneal furnace, back grind equipment for thinning SiC wafers, backside metal sputter and backside laser anneal tools. X-FAB can, as a result, now fully leverage the economies of scale that are already available in its established 30K wafer per month silicon line, thereby presenting the market with the means to produce large volumes of SiC devices on 6-inch wafers.

As well as X-FAB’s 6-inch wafer capabilities, X-FAB will supply fabless semiconductor vendors, the company will also be well positioned to serve as a second source solution for IDMs with their own SiC manufacturing.

Current SiC offerings are either IDMs creating their own products or relatively small foundry operations using 4-inch production facilities, X-FAB is bringing something different to the market, with a SiC capacity of 5k wafers/month ready to utilize and potential to raise this further. We can thus offer a scalable, high quality, secure platform that will enable customers to cost-effectively obtain discrete devices on SiC substrates and also safely apply vital differentiation."


Innovation Award

MOSFET scaling has for several decades been the main path to increase the performance of Si CMOS technology. As a result, the transistor density in the circuits has steadily increased. Since the subthreshold swing (S) for a thermionic device does not scale below 60 mV/dec., this has resulted in increased power density, which has become the main limitation.

To achieve voltage scaling without off-current increase, there is a need for devices with a subthreshold swing lower than 60mV/dec.. These are so called steep slope devices, of which the Tunneling Field-Effect Transistor (TFET) is the most promising candidate [1-2]. The TFET operation rely on tunneling-based energy filtering that prevents electrons with high thermal energy to enter the channel thereby enabling sub-60 mV/dec. subthreshold swing. So far, few reports exist of TFETs with S below 60 mV/dec. usually with current levels far below any useful operation range [3-8]. We here present a vertical nanowire InAs/GaAsSb/GaSb heterojunction TFET integrated on a Si substrate with Smin = 48 mV/dec. with I60 = 0.31 μA/μm at VDS = 0.3 V and IDS = 10.6 μA/μm for Ioff = 1nA/um at VDS = 0.3 V. The device achieves an intrinsic gain of 2400 and a transconductance efficiency of 50 V-1. Our novel heterostructure design enabled by the reduced constraint for lattice matching in the bottom up nanowire growth in combination with aggressively scaled dimensions and a gateall-around geometry demonstrate that III-V TFETs are viable alternative both for low-power logic and analog applications.

[1] A.C. Seabaugh, Q. Zhang, Proc. IEEE, Vol. 98, No. 12, pp. 2095–2110, 2010
[2] A. M. Ionescu, H. Riel, Nature, Vol. 479, No. 7373, pp. 329–337, 2011
[3] Q. Huang et. al., in Electron Devices Meeting (IEDM), 2012 IEEE International, pp. 8.5.1 – 8.5.4
[4] L. Knoll et. al., Electron Device Letters, IEEE, Vol. 34, no. 6, pp. 813 – 815, 2013
[5] S. H. Kim et. al., in Proc. VLSI Symp.Tech. Dig., 2012, pp. 178-179
[6] K. Tomioka et. al., in Proc. VLSI Symp.Tech. Dig., 2012, pp. 47-48
[7] T. Krishnamohan et. al., in Electron Devices Meeting (IEDM), 2008 IEEE International, pp. 947 – 949
[8] G. Dewey et. al., in Electron Devices Meeting (IEDM), 2011 IEEE International, pp. 33.6.1–33.6.4

Scientists at IBM Research GmbH achieved the first demonstration of an InGaAs/SiGe CMOS technology on Si substrate using processes suitable for high-volume manufacturing on 300 mm wafers. InGaAs/SiGe hybrid integration is the main path to enable further improvement of power/performance trade off metrics for digital technologies beyond the 7 nm node. Based on selective epitaxy their approach yielded functional inverters and dense arrays of 6T-SRAMs the basic blocks of digital CMOS circuits.

This work – first of a kind – has been disclosed at the last VLSI Technology conference. It concludes a series of key demonstrations for InGaAs/SiGe CMOS reported in multiple contributions and highlights for the last four years at IEDM meetings and VLSI Technology Symposia. Since many years the technological bottleneck is to demonstrate a path that enable simultaneously the growth of defect-free InGaAs the fabrication of high performance InGaAs field effect transistors “on-insulator” and their co-processing with SiGe devices all on a silicon substrate.

A few approaches have been proposed but the work nominated is the only one that reports basic building blocks of digital circuits at relevant dimensions and achieves a major milestone towards a manufacturable hybrid InGaAs/SiGe CMOS technology. It features in a single technology the selective growth of high quality InGaAs-on-Insulator regions the fabrication of InGaAs finFETs with physical gate length Lg= 35nm and good device characteristics and the processing of functional 6T-SRAM cells with a cell area ≈0.4mµ2. All metrics compare favourably to industrial state-of-the-art numbers (e.g. ≈0.1µm2 for an SRAM cells in 22 nm technology. It clearly highlights the potential of the nominated work as the method of choice to co-integrate InGaAs and SiGe MOSFETs for advanced CMOS technology. It also opens the door towards future low cost RF or photonic circuits based on a similar hybrid III-V silicon technologies.





Key Dates 2016/2017

Nominations open 25th November 2016
Nominations close 9th January 2017
Shortlist announced 16th January 2017
Voting opens 16th January 2017
Voting closes 21st February 2017
Winners informed 21st February 2017
Awards ceremony 7th March 2017

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